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ics9fg1201h idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 frequency gearing clock for cpu, pci e gen1, gen2, & fbd da t asheet 1 description the ics9fg1201h follows the intel db1200g rev 1.0 differential buff er specification. this b uff er pro vides 12 output cloc ks f or cpu host bus , pci-express , or fully buff ered dimm applications . the outputs are configured with two groups. both groups (dif 9:0) and(dif 11:10) can be equal to or have a gear ratio to the input clock. a differential cpu clock from a ck410b or ck410b+ main clock gener ator , such as the ics932s421, dr iv es the ics9fg1201. the ics9fg1201h can provide outputs up to 400mhz ke y specifications ? dif output cycle-to-cycle jitter < 50ps ? dif output-to-output sk e w < 50ps within a g roup ? dif output-to-output sk e w < 100ps across all outputs ? 56-pin ssop/tssop pac kage ? rohs compliant packaging features/benefits? drives 2 channels of 4 fbdimms (total of 8 fbdimms) ? pow er up def ault is all outputs in 1:1 mode ? dif_(9:0) can be ?gear-shifted? from the input cpu hostcloc k ? dif_(11:10) can be ?gear-shifted? from the input cpu host cloc k ? spread spectr um compatib le ? suppor ts output cloc k frequencies up to 400 mhz ? 8 selectab le smbus addresses ? smbus address deter mines pll or bypass mode functional block diagram stop logic clk_in clk_in# dif(9:0) control logic high_bw# smb_a2_pllbyp# smbdat smbclk vtt_pwrgd#/pd spread compatible pll 10 iref oe(9:0)# 10 smb_a0 smb_a1 fs_a_410 stop logic dif(11:10) 2 oe# gear shift logic spread compatible pll gear shift logic
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 2 pin configurationfunctionality t ab le 56-pin ssop & tssop fs_a_410 1 clk_in (cpu fsb) mhz dif_(9:0) output mhz dif_(11:10) output mhz 1 100.00 100.00 100.00 1 133.33 133.33 133.33 1 166.66 166.66 166.66 1 0 200.00 200.00 200.00 0 266.66 266.66 266.66 0 333.33 333.33 333.33 0 400.00 400.00 400.00 1. fs_a_410 is a low-threshold input. please see t he v il_fs and v ih_fs specifications in the input/supply/common output pa rameters table for correct values. reserved high_bw# 1 56 vdda clk_in 2 55 gnda clk_in# 3 54 iref smb_a0 4 53 oe10_11# oe0# 5 52 dif_11 dif_0 6 51 dif_11# dif_0# 7 50 vdd oe1# 8 49 gnd dif_1 9 48 dif_10 dif_1# 10 47 dif_10# vdd 11 46 fs_a_410 gnd 12 45 vtt_pwrgd#/pd dif_2 13 44 oe9# dif_2# 14 43 dif_9 oe2# 15 42 dif_9# dif_3 16 41 oe8# dif_3# 17 40 dif_8 oe3# 18 39 dif_8# dif_4 19 38 vdd dif_4# 20 37 gnd oe4# 21 36 dif_7 vdd 22 35 dif_7# gnd 23 34 oe7# dif_5 24 33 dif_6 dif_5# 25 32 dif_6# oe5# 26 31 oe6# smb_a1 27 30 smb_a2_pllbyp# smbdat 28 29 smbclk ics9fg1201h
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 3 pin description po wer gr oups vdd gnd 56 55 main pll, analog 11,22,38,50 12,23,37,49 dif clocks description pin number pin # pin name type pin description 1 high_bw# in 3.3v input for selecting pll band width 0 = high, 1= low 2 clk_in in input for reference clock. 3 clk_in# in "complementary" reference clock input. 4 smb_a0 in smbus address bit 0 (lsb) 5 oe0# in active low input for enabling dif pair 0. 1 = tri-state outputs, 0 = enable outputs 6 dif_0 out 0.7v differential true clock output 7 dif_0# out 0.7v differential complement clock output 8 oe1# in active low input for enabling dif pair 1. 1 = tri-state outputs, 0 = enable outputs 9 dif_1 out 0.7v differential true clock output 10 dif_1# out 0.7v differential complement clock outpu t 11 vdd pwr power supply, nominal 3.3v 12 gnd pwr ground pin. 13 dif_2 out 0.7v differential true clock output 14 dif_2# out 0.7v differential complement clock outpu t 15 oe2# in active low input for enabling dif pair 2. 1 = tri-state outputs, 0 = enable outputs 16 dif_3 out 0.7v differential true clock output 17 dif_3# out 0.7v differential complement clock outpu t 18 oe3# in active low input for enabling dif pair 3. 1 = tri-state outputs, 0 = enable outputs 19 dif_4 out 0.7v differential true clock output 20 dif_4# out 0.7v differential complement clock outpu t 21 oe4# in active low input for enabling dif pair 4 1 = tri-state outputs, 0 = enable outputs 22 vdd pwr power supply, nominal 3.3v 23 gnd pwr ground pin. 24 dif_5 out 0.7v differential true clock output 25 dif_5# out 0.7v differential complement clock outpu t 26 oe5# in active low input for enabling dif pair 5. 1 = tri-state outputs, 0 = enable outputs 27 smb_a1 in smbus address bit 1 28 smbdat i/o data pin of smbus circuitry, 5v tolerant
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 4 pin description (contin ued) pin # pin name type pin description 29 smbclk in clock pin of smbus circuitry, 5v tolerant 30 smb_a2_pllbyp# in smbus address bit 2. when low, the part operates as a fanout buffer with the pll bypassed. when high, the part operates as a zero-delay buffer (zdb) with the pll operating. 0 = fanout mode (pll bypassed), 1 = zdb mode (pll u sed) 31 oe6# in active low input for enabling dif pair 6. 1 = tri-state outputs, 0 = enable outputs 32 dif_6# out 0.7v differential complement clock outpu t 33 dif_6 out 0.7v differential true clock output 34 oe7# in active low input for enabling dif pair 7. 1 = tri-state outputs, 0 = enable outputs 35 dif_7# out 0.7v differential complement clock outpu t 36 dif_7 out 0.7v differential true clock output 37 gnd pwr ground pin. 38 vdd pwr power supply, nominal 3.3v 39 dif_8# out 0.7v differential complement clock outpu t 40 dif_8 out 0.7v differential true clock output 41 oe8# in active low input for enabling dif pair 8. 1 = tri-state outputs, 0 = enable outputs 42 dif_9# out 0.7v differential complement clock outpu t 43 dif_9 out 0.7v differential true clock output 44 oe9# in active low input for enabling dif pair 9. 1 = tri-state outputs, 0 = enable outputs 45 vtt_pwrgd#/pd in vtt_pwrgd# is an active low input used to determine when latched inputs are ready to be sampled. pd is an asynchrono us active high input pin used to put the device into a low power s tate. the internal clocks, plls and the crystal oscillator are stopped . 46 fs_a_410 in 3.3v tolerant low threshold input for cpu frequenc y selection. this pin requires ck410 fsa. refer to input electrical c haracteristics for vil_fs and vih_fs threshold values. 47 dif_10# out 0.7v differential complement clock outp ut 48 dif_10 out 0.7v differential true clock output 49 gnd pwr ground pin. 50 vdd pwr power supply, nominal 3.3v 51 dif_11# out 0.7v differential complement clock outp ut 52 dif_11 out 0.7v differential true clock output 53 oe10_11# in active low input for enabling output pairs 10 and 1 1. 1 = tri-state outputs, 0 = enable outputs 54 iref out this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed preci sion resistor tied to ground in order to establish the appropriate curren t. 475 ohms is the standard value. 55 gnda pwr ground pin for the pll core. 56 vdda pwr 3.3v power for the pll core.
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 5 bit 3 bit 2 bit 1 bit 0 200.0 266.7 320.0 333.3 400.0 0 0 0 0 0 3 1 0.333 66.7 88.9 106.7 111.1 133.3 0 0 0 0 1 5 2 0.400 80.0 106.7 128.0 133.3 160.0 0 0 0 1 0 12 5 0.417 83.3 111.1 133.3 138.9 166.7 0 0 0 1 1 2 1 0.500 100.0 133.3 160.0 166.7 200.0 0 0 1 0 0 5 3 0.600 120.0 160.0 192.0 200.0 240.0 0 0 1 0 1 8 5 0.625 125.0 166.7 200.0 208.3 250.0 0 0 1 1 0 3 2 0.667 133.3 177.8 213.3 222.2 266.7 0 0 1 1 1 4 3 0.750 150.0 200.0 240.0 250.0 300.0 0 1 0 0 0 6 5 0.833 166.7 222.2 266.7 277.8 333.3 0 1 0 0 1 1 1 1.000 200.0 266.7 320.0 333.3 400.0 0 1 0 1 0 5 6 1.200 240.0 320.0 384.0 400.0 na 0 1 0 1 1 4 5 1.250 250.0 333.3 400.0 na na 0 1 1 0 0 3 4 1.333 266.7 355.6 na na na 0 1 1 0 1 2 3 1.500 300.0 400.0 na na na 0 1 1 1 0 3 5 1.667 333.3 na na na na 0 1 1 1 1 1 2 2.000 400.0 na na na na 100 133.33 160 166.67 1 0 0 0 0 3 1 0.333 1 0 0 0 1 5 2 0.400 na 53.3 64.0 66.7 1 0 0 1 0 12 5 0.417 na 55.6 66.7 69.4 1 0 0 1 1 2 1 0.500 50.0 66.7 80.0 83.3 1 0 1 0 0 5 3 0.600 60.0 80.0 96.0 100.0 1 0 1 0 1 8 5 0.625 62.5 83.3 100.0 104.2 1 0 1 1 0 3 2 0.667 66.7 88.9 106.7 111.1 1 0 1 1 1 5 4 0.800 80.0 106.7 128.0 133.3 1 1 0 0 0 6 5 0.833 na 111.1 133.3 138.9 1 1 0 0 1 1 1 1.000 100.0 133.3 160.0 166.7 1 1 0 1 0 5 6 1.200 120.0 160.0 192.0 200.0 1 1 0 1 1 4 5 1.250 125.0 166.7 200.0 208.3 1 1 1 0 0 3 4 1.333 133.3 177.8 213.3 222.2 1 1 1 0 1 2 3 1.500 150.0 200.0 1 1 1 1 0 3 5 1.667 166.7 222.2 266.7 277.8 1 1 1 1 1 1 2 2.000 200.0 266.7 320.0 333.3 shaded areas are shown for reference only and are n ot necessarily valid operating points note: lines in bold are power-up defaults for fs_a_410 = 0 and 1 respe ctively. clk in (cpu fsb) frequency (mhz) output (n) gear ratio (n/m) smbus byte 0 ics9fg1201 programmable gear ratios fs_a_410 input (cpu fsb) and output frequencies (mhz) input (m)
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 6 byte 8, bit 2 fsc byte 8, bit 1 fsb byte 8, bit 0 fs_a_410 clk_in (cpu fsb) mhz 1:1 dif outputs mhz notes 1 0 1 100.00 100.00 3 0 0 1 133.33 133.33 3 0 1 1 166.67 166.67 1 0 1 0 200.00 200.00 3 0 0 0 266.67 266.67 3 1 0 0 333.33 333.33 3 1 1 0 400.00 400.00 2 1 1 1 notes:fs_a_410 = 1 1. powerup default for fs_a_410 = 1 2. powerup default for fs_a_410 = 0 3. setting the exact fsb frequency after power up i s required for best phase noise performance. reserved ics 9fg1201h 1:1 pll programming
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 7 9fg1201/2 smbus address mapping when using ck410b+ and db400/800 smb adr: dc 9db401/801 (db400/800) pll bypass mode smb_a2_pllbyp# = 0 pll zdb mode smb_a2_pllbyp# = 1 or or smb_a(2:0) = 100 smb adr: d8 9fg1201/2 (db1200g) smb_a(2:0) = 101 smb adr: da 9fg1201/2 (db1200g) smb_a(2:0) = 110 smb adr: dc 9fg1201/2 (db1200g) smb_a(2:0) = 111 smb adr: de 9fg1201/2 (db1200g) smb_a(2:0) = 000 smb adr: d0 9fg1201/2 (db1200g) smb_a(2:0) = 001 smb adr: d2 9fg1201/2 (db1200g) smb_a(2:0) = 010 smb adr: d4 9fg1201/2 (db1200g) smb_a(2:0) = 011 smb adr: d6 9fg1201/2 (db1200g) smb adr: d2 932s421 (ck410b+) `
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 8 general smbus serial interface inf ormation f or the ics9fg1201h ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the wr ite address d0 (h) ? ics cloc k will ac kno wledg e ? controller (host) sends the begining b yte location = n ? ics cloc k will ac kno wledg e ? controller (host) sends the data b yte count = x ? ics cloc k will ac kno wledg e ? controller (host) star ts sending byte n thr ough byte n + x -1 ? ics cloc k will ac kno wledg e each b yte one at a time ? controller (host) sends a stop bit ho w to read: ? controller (host) will send star t bit. ? controller (host) sends the wr ite address d0 (h) ? ics cloc k will ac kno wledg e ? controller (host) sends the begining b yte location = n ? ics cloc k will ac kno wledg e ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address d1 (h) ? ics cloc k will ac kno wledg e ? ics cloc k will send the data b yte count = x ? ics cloc k sends byte n + x -1 ? ics cloc k sends byte 0 thr ough b yte x (if x (h) was written to b yte 8) . ? controller (host) will need to ac kno wledge each b yte ? controllor (host) will send a not ac kno wledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d0 (h) * beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d1 (h) * index block read operation slave address d0 (h) * beginning byte = n ack ack * note: see smbus address mapping (page 7), for programming smbus read/write address
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 9 smbustable: gear ratio select register pin # name control function type 0 1 pwd bit 7 rw gear ratio 1:1 1 bit 6 rw gear ratio 1:1 1 bit 5 rw 1 bit 4 rw latch bit 3 rw 1 bit 2 rw 0 bit 1 rw 1 bit 0 rw 1 smbustable: output control register pin # name control function type 0 1 pwd bit 7 dif_7 output control rw hi-z enable 1 bit 6 dif_6 output control rw hi-z enable 1 bit 5 dif_5 output control rw hi-z enable 1 bit 4 dif_4 output control rw hi-z enable 1 bit 3 dif_3 output control rw hi-z enable 1 bit 2 dif_2 output control rw hi-z enable 1 bit 1 dif_1 output control rw hi-z enable 1 bit 0 dif_0 output control rw hi-z enable 1 smbustable: output and pll bw control register pin # name control function type 0 1 pwd bit 7 1 bit 6 rw high bw low bw 1 bit 5 rw bypass pll 1 bit 4 1 bit 3 dif_11 output control rw hi-z enable 1 bit 2 dif_10 output control rw hi-z enable 1 bit 1 dif_9 output control rw hi-z enable 1 bit 0 dif_8 output control rw hi-z enable 1 note: bit 6 is wired or to the pin 1 input, any 0 s elects high bw note: bit 5 is wired or to the pin 30 input, any 0 selects fanout bypass mode smbustable: output enable readback register pin # name control function type 0 1 pwd bit 7 r x bit 6 r x bit 5 r x bit 4 r x bit 3 r x bit 2 r x bit 1 r x bit 0 r x byte 3 readback - oe7# input readback readback readback readback readback readback - oe1# input readback see note pll_bw# adjust see note 51,52 47,48 31 readback - oe6# input readback - oe3# input readback - oe5# input readback - oe4# input readback - oe2# input 5 readback - oe0# input 16,17 13,14 9,10 6,7 see 9fg1201 programmable gear ratios table - gear ratio fs3 - gear ratio fs2 - gear ratio fs1 - gear ratio fs0 group of 10 gear ratio enable dif(11:10) group of 2 gear ratio enable - gear ratio fs4 (fs_a_410) - reserved byte 0 dif(9:0) byte 1 35, 36 32, 33 24, 25 19,20 34 26 21 18 8 15 readback byte 2 reserved reserved 39,40 readback bypass# test mode / pll 42,43
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 10 smbustable: output enable readback register pin # name control function type 0 1 pwd bit 7 r x bit 6 r x bit 5 r x bit 4 r x bit 3 r x bit 2 r x bit 1 r x bit 0 r x smbustable: vendor & revision id register pin # name control function type 0 1 pwd bit 7 rid3 r - - x bit 6 rid2 r - - x bit 5 rid1 r - - x bit 4 rid0 r - - x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id pin # name control function type 0 1 pwd bit 7 rw 1 bit 6 rw 1 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 0 bit 0 rw 1 smbustable: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 1 bit 2 bc2 rw - - 0 bit 1 bc1 rw - - 0 bit 0 bc0 rw - - 1 reserved device id 2 reserved device id 1 reserved reserved readback readback - oe10_11# input readback readback device id 7 (msb) reserved readback - smb_a2_pllbyp# in readback reserved readback readback - oe8# input readback 44 41 device id 6 byte 6 -- readback - oe9# input revision id - - 30 53 readback readback - high_bw# in - - vendor id -- - 1 readback 46 readback - fs_a_410 byte 4 - - - -- - - - - - - - - - byte 7 - byte 5 writing to this register configures how many bytes will be read back. reserved device id 5 reserved device id 4 reserved device id 3 reserved device id 0
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 11 smbustable: 1:1 pll frequency selection pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 rw x bit 1 rw 1 bit 0 rw latch smbustable: reserved register pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: m/n programming enable pin # name control function type 0 1 pwd bit 7 m/n_en gear pll and 1:1 pll m/n programming enable rw disable enable 0 bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x smbus table: gear pll frequency control register pin # name control function type 0 1 pwd bit 7 x bit 6 x bit 5 gear pll m div5 rw x bit 4 gear pll m div4 rw x bit 3 gear pll m div3 rw x bit 2 gear pll m div2 rw x bit 1 gear pll m div1 rw x bit 0 gear pll m div0 rw x reserved reserved see 9fg1201h m/n programming table reserved reserved reserved m divider programming bits reserved reserved reserved reserved reserved see 9fg1201h 1:1 pll programming table reserved frequency select c frequency select b fs_a_410 reserved reserved reserved reserved reserved reserved - - -- byte 8 - reserved byte 11 -- - - byte 10 - reserved reserved reserved reserved byte 9
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 12 smbus table: gear pll frequency control register pin # name control function type 0 1 pwd bit 7 gear pll n div7 rw x bit 6 gear pll n div6 rw x bit 5 gear pll n div5 rw x bit 4 gear pll n div4 rw x bit 3 gear pll n div3 rw x bit 2 gear pll n div2 rw x bit 1 gear pll n div1 rw x bit 0 gear pll n div0 rw x smbustable: gear pll output divider register pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 goutdiv 3 rw x bit 2 goutdiv 2 rw x bit 1 goutdiv 1 rw x bit 0 goutdiv 1 rw x smbustable: reserved register pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbustable: reserved register pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved reserved byte 15 byte 13 byte 14 - reserved reserved reserved reserved see gear output divider table gear output divider reserved n divider programming bits reserved reserved reserved see 9fg1201h m/n programming table reserved reserved reserved reserved reserved - - - byte 12 -- - - reserved reserved reserved reserved
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 13 smbustable: reserved register pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: 1:1 pll frequency control register pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 1:1 pll m div5 rw x bit 4 1:1 pll m div4 rw x bit 3 1:1 pll m div3 rw x bit 2 1:1 pll m div2 rw x bit 1 1:1 pll m div1 rw x bit 0 1:1 pll m div0 rw x smbus table: 1:1 pll frequency control register pin # name control function type 0 1 pwd bit 7 1:1 pll n div7 rw x bit 6 1:1 pll n div6 rw x bit 5 1:1 pll n div5 rw x bit 4 1:1 pll n div4 rw x bit 3 1:1 pll n div3 rw x bit 2 1:1 pll n div2 rw x bit 1 1:1 pll n div1 rw x bit 0 1:1 pll n div0 rw x smbustable: 1:1 pll output divider register pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 1outdiv 3 rw x bit 2 1outdiv 2 rw x bit 1 1outdiv 1 rw x bit 0 1outdiv 1 rw x m divider programming bits -- byte 16 byte 17 - - - - byte 18 - -- - - -- byte 19 - reserved reserved reserved n divider programming bits reserved reserved reserved see 9fg1201h m/n programming table reserved reserved reserved 1:1 output divider see 1:1 output divider table reserved see 9fg1201h m/n programming table reserved reserved reserved reserved
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 14 smbustable: reserved register pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbustable: test byte register test type pwd bit 7 rw 0 bit 6 rw 0 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 0 bit 0 rw 0 note: do not write to bit 21. erratic device opera tion will result! ics only test reserved ics only test reserved ics only test reserved ics only test reserved ics only test reserved ics only test reserved ` ics only test reserved ics only test reserved byte 21 test function reserved reserved test result reserved reserved reserved reserved byte 20 reserved reserved
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 15 absolute maxelectrical characteristics - input/suppl y/common output p arameter s parameter symbol conditions min typ max units notes 3.3v core supply voltage vdd_a gnd - 0.5 v dd + 0.5v v 1 3.3v logic supply voltage vdd_in gnd - 0.5 v dd + 0.5v v 1 storage temperature ts -65 150 c 1 ambient operating temp tambient 0 70 c 1 case temperature tcase 115 c 1 input esd protection esd prot human body model 2000 v 1 t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5%, except clk_in 2 v dd + 0.3 v 1 input low voltage v il 3.3 v +/-5%, except clk_in v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua input low current i il1 v in = 0 v; inputs with no pull- up resistors -5 ua low threshold input- high voltage v ih_fs 3.3 v +/-5%, applies to fs_a_410 pin 0.7 v dd + 0.3 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5%, applies to fs_a_410 pin v ss - 0.3 0.35 v 1 operating current i dd3.3op all outputs driven 375 ma 1 powerdown current i dd3.3pd all differential pairs tri-stated 24 ma 1 input frequency f i v dd = 3.3 v 100 400 mhz 3 pin inductance l pin 7 nh 1 c in logic inputs 5 pf 1 c out output pin capacitance 5 pf 1 clk stabilization t stab from v dd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 modulation frequency triangular modulation 30 33 khz 1 tdrive_pd# dif output enable after pd# de-assertion 300 us 1 tfall_pd# pd# fall time of 5 ns 1 trise_pd# pd# rise time of 5 ns 2 smbus voltage v max maximum input voltage 5.5 v 1 low-level output voltage v ol @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 input capacitance
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 16 electrical characteristics - dif 0.7v current mode diff erential p air t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 , r p =49.9 , ref = 475 parameter symbol conditions min typ max units notes current source output impedance zo 1 v o = v x 3000 1 voltage high vhigh 660 850 1,3 voltage low vlow -150 150 1,3 max voltage vovs 1150 1 min voltage vuds -300 1 crossing voltage (abs) vcross(abs ) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all edges 140 mv 1 long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 400mhz nominal 2.4993 2.5008 ns 2 400mhz spread 2.4993 2.5133 ns 2 333.33mhz nominal 2.9991 3.0009 ns 2 333.33mhz spread 2.9991 3.016 ns 2 266.66mhz nominal 3.7489 3.7511 ns 2 266.66mhz spread 3.7489 3.77 ns 2 200mhz nominal 4.9985 5.0015 ns 2 200mhz spread 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz spread 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz spread 7.4978 7.5400 ns 2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2 400mhz nominal/spread 2.4143 ns 1,2 333.33mhz nominal/spread 2.9141 ns 1,2 266.66mhz nominal/spread 3.6639 ns 1,2 200mhz nominal/spread 4.8735 ns 1,2 166.66mhz nominal/spread 5.8732 ns 1,2 133.33mhz nominal/spread 7.3728 ns 1,2 100.00mhz nominal/spread 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 t jcyc-cyc pll mode, from differential wavefrom 50 ps 1,4,5 t jbyp bypass mode as additive jitter 50 ps 1,4 notes: 1.guaranteed by design and characterization, not 10 0% tested in production. 3.iref = vdd/(3xrr). for rr = 475 (1%), iref = 2.32ma. ioh = 6 x iref and voh = 0.7v @ zo=50 . 4. measured into fixed 2 pf load cap. input to output skew is measured at the first output edge followin g the corresponding input. 5. measured from differential cross-point to different ial cross-point 6. all bypass mode input-to-output specs refer to t he timing between an input edge and the specific ou tput edge created by it. jitter, cycle to cycle 2. all long term accuracy and clock period specific ations are guaranteed assuming that the input frequ ency meets ck410b accuracy requirements absolute min period t absmin average period tperiod measurement on single ended signal using absolute value. mv statistical measurement on single ended signal using oscilloscope math function. mv
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 17 electrical characteristics - skew and differential jitter parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% group parameter description min typ max units notes clk_in, dif[x:0] t spo_pll input-to-output skew in pll mode (1:1 only), nominal value @ 25 c , 3 . 3 v -500 140 500 ps 1,2,4,5,8, 12 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode (1:1 only), nominal value @ 25 c , 3 . 3 v 2.5 3.1 4.5 ns 1,2,3,5, 12 clk_in, dif [x:0] ? t spo_pll input-to-output skew variation in pll mode (over specified voltage / temperature operating ran ges) 270 |350| ps 1,2,4,5,6, 10,12 clk_in, dif [x:0] ? t pd_byp input-to-output skew variation in bypass mode (over specified voltage / temperature operating ran ges) 470 |500| ps 1,2,3,4,5, 6,10,12 dif[11:10] t skew_g2 output-to-output skew group of 2 (common to bypass and pll mode) 10 25 ps 1,2,12 dif[9:0] t skew_g10 output-to-output skew group of 10 (common to bypass and pll mode) 40 50 ps 1,2,12 dif[11:0] t skew_a12 output-to-output skew across all 12 outputs (common to bypass and pll mode - all outputs at same gear) 80 100 ps 1,2,3,12 dif[11:0] t jph differential phase jitter (rms value) 5 10 ps 1,4,7,12 dif[11:0] t ssterror differential spread spectrum tracking error (peak t o peak) 40 80 ps 1,4,9,12 pll jitter peaking j peak-hibw (high_bw# = 0) 0 2 2.5 db 11,12 pll jitter peaking j peak-lobw (high_bw# = 1) 0 1.3 2 db 11,12 pll bandwidth pll hibw (high_bw# = 0) 2 3.6 4 mhz 12,13 pll bandwidth pll lobw (high_bw# = 1) 0.7 1.2 1.4 mhz 12,13 notes on skew and differential jitter parameters: 8. t is the period of the input clock 11. measured as maximum pass band gain. at frequencies within the loop bw, highest point of magnification is called pll jitter peaking. 12. guaranteed by design and characterization, not 100% tested in production. 13. measured at 3 db down or half power point. 1. measured into fixed 2 pf load cap. input to ou tput skew is measured at the first output edge foll owing the corresponding input. 2. measured from differential cross-point to diffe rential cross-point 10. this parameter is an absolute value. it is not a double-sided figure. 9. differential spread spectrum tracking error is t he difference in spread spectrum tracking between t wo 9fg1201h devices this parameter is measured at the outputs of two separate 9fg1201h devices driven by a single ck410b + in spread spectrum mode. the 9fg1201h must set t o high bandwidth. the spread spectrum characterisi tics are : maximum of 0.5%, 30 to 33khz modulation frequency, linear profile. 5. measured with scope averaging on to find mean v alue. 6. long-term variation from nominal of input-to-ou tput skew over temperature and voltage for a single device. 7. this parameter is measured at the outputs of two separate 9fg1201h devices driven by a single ck410 b+. the 9fg1201h must be set to high bandwidth. di fferential phase jitter is the accumulation of the phase jitte r not shared by the outputs (eg. not including the affects of spread spectrum). target ranges of cons ideration are agents with bw of 1-22mhz and 11-33mhz. 3. all bypass mode input-to-output specs refer to the timing between an input edge and the specific o utput edge created by it. 4. this parameter is deterministic for a given devi ce
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 18 electrical characteristics - phase jitter parameter symbol conditions min typ. max units notes t jphpcie1 pcie gen 1 refclk phase jitter (including pll bw 8 - 16 mhz, = 0.54, td=10 ns, ftrk=1.5 mhz ) 40/38 86 ps 1,2,3,5 t jphpcie2lo pcie gen 2 refclk phase jitter (including pll bw 8 - 16 mhz, = 0.54, td=12 ns) lo-band content (10khz to 1.5mhz) 1.3/1.2 3 ps rms 1,2,5 t jphpcie2hi pcie gen 2 refclk phase jitter (including pll bw 8 - 16 mhz, = 0.54, td=12 ns) hi-band content (1.5mhz to nyquist) 3.0/2.4 3.1 ps rms 1,2,5 t jphfbd1_3.2g fbd refclk phase jitter (including pll bw 11 - 33 mhz, = 0.54, td=12 ns ftrl=0.2mhz) 2.8/2.3 3 ps (rms) 1,2,5 t jphfbd1_4.8g fbd refclk phase jitter (including pll bw 11 - 33 mhz, = 0.54, td=12 ns ftrl=0.2mhz) 2.3/1.9 2.5 ps (rms) 1,2,5 notes on phase jitter: 2 device driven by 932s421bglf or equivalent 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1 -12 4 hi-bandwidth number/low bandwidth number with spre ad on. spread off gives lower numbers. 5 byte 8 must be properly set to meet these paramete rs. 1 see http://www.pcisig.com for complete specs. guar anteed by design and characterization, not tested i n production. jitter, phase
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 19 common recommendations for differential routing dime nsion or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max i nch 1 l2 length, route as non-coupled 50ohm trace 0.2 max i nch 1 l3 length, route as non-coupled 50ohm trace 0.2 max i nch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm diffe rential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differ ential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm diffe rential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differ ential trace 0.225 min to 12.6 max inch 2 src reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 20 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compati ble 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common d ifferential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 21 indexarea 1 2 n d h x 45 e1 e seating plane a1 a e - c - b .10 (.004) c c l min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 variations min max min max 56 18.31 18.55 .720 .730 10-0034 reference doc.: jedec publication 95, mo-118 56-lead, 300 mil body, 25 mil, ssop n see variations see variations d mm. d (inch) symbol see variations see variations 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions
idt tm /ics tm frequency gearing clock for cpu, pci e gen1, gen2, & fbd 1371f ? 09/23/09 ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 22 indexarea 1 2 n d e1 e a seating plane a1 a a2 e - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 de e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 56 13.90 14.10 .547 .555 10-0039 n d mm. d (inch) ref erence doc.: jedec publicat ion 95, m o-153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic 56-lead 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (2 0 mil) symbol in millimeters in inches common dimensions common dimensions ordering information part / order number shipping/packaging package tempera ture 9fg1201hglf tubes 56-pin tssop 0 to +70c 9fg1201hglft tape and reel 56-pin tssop 0 to +70c 9FG1201HFLF tubes 56-pin ssop 0 to +70c 9FG1201HFLFt tape and reel 56-pin ssop 0 to +70c "lf" denotes pb free packaging, rohs compliant "h" denotes revision designator (will not correlate with datasheet revision)
ics9fg1201h frequency gearing clock for cpu, pcie gen1, gen2, & fbd 23 innovate with idt and accelerate your future networks. cont act: www .idt .com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for t ech support 408-284-6578 pcclockhelp@id t.com corporate headquarters integrated device t echnology , inc. 6024 silver creek v alley road san jose, ca 95138 united s t ates 800 345 7015 +408 284 8200 (out side u.s.) asia pacific and jap an integrated device t echnology singapore (1997) pte. lt d. reg. no. 199707558g 435 orchard road #20-03 w isma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett w ood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device t echnology , inc. all right s reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device t echnology , inc. accelerated thinking is a service mark of integrated device t echnology , inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify product s or services of their respective owners. printed in usa tm revision history rev. issue date description page # a 10/22/2007 release to final. - b 1/29/2008 updated key specifications: changed units for dif output-to-output skew to "ps" . 1 c 2/12/2008 changed cin value from 6 pf to 5 pf. 14 d 9/24/2008 added 1:1 vco programming table 6 e 1/21/2009 updated skew and phase jitter tables. 17,1 8 f 9/23/2009 updated ordering information table 22

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